Many product designs are a series of compromises. Take for example, electric vehicles, wouldn’t it be great to have a 1000-mile or 1600-kilometer range in an EV? But consider what compromises would need to be made to achieve this goal. The battery would be massive and heavy, leading to an overall decrease in efficiency as you haul around the extra weight, which also affects acceleration and handling. Such a car would also be extremely expensive because of the massive battery pack. A reasonable compromise would be to have a smaller battery pack and focus on aerodynamic and motor efficiencies to maximize range but also focus on rapid charging to minimize any inconveniences.
In the chip world, all products are a series of choices and compromises, designed with a careful balance of performance, power efficiency and size (cost). One of the most basic choices for a product designer is the choice of which semiconductor process technology to use. Does a designer choose a high-performance technology at a higher supply voltage for maximum frequency and performance? This performance bias would also create a larger die area, consume a lot more power and generate more heat. Does a designer choose a more balanced technology that can be smaller in size, consume less power but will not be able to hit the highest frequencies? Or do they select a technology that focuses on the best power efficiency and the lowest leakage? Chip designers had to make these tough choices prior to the arrival of TSMC’s N3 technology.
TSMC is pleased to introduce FINFLEX for N3 at our 2022 Symposium. TSMC FINFLEX™ extends the product performance, power efficiency and density envelope of the 3nm family of semiconductor technologies by allowing chip designers to choose the best option for each of the key functional blocks on the same die using the same design toolset. These options include a 3-2 FIN, 2-2 FIN and 2-1 FIN configuration with the following characteristics:
3-2 FIN – Fastest clock frequencies and highest performance for the most demanding compute needs
2-2 FIN – Efficient Performance, a good balance between performance, power efficiency and density
2-1 FIN – Ultra Power Efficiency, lowest power consumption, lowest leakage and highest density
Diagram 1: N3 with FINFLEX delivers maximum flexibility and gives chip designers the ideal characteristics for each of the key functional blocks on the same die, with the same design toolset.
One recent product trend is that of Hybrid CPUs. These new CPUs feature high-performance CPU cores mated with power efficient CPU cores along with GPU cores and fixed function blocks. The power efficient CPU cores handle most of the everyday workloads. As the workloads increase, the high-performance cores activate. Complementing these CPU cores are ultra-efficient and ultra-dense GPU and fixed function blocks. With TSMC FINFLEX™ in N3, product designers can choose the best FIN configuration for each of these functional blocks, optimizing each block without affecting others, all on the same die.
Diagram 2: N3 with FINFLEX enables a designer to choose the ideal FIN configuration for each functional block on a chip.
TSMC’s N3 transistor leads the 3-nanometer generation of semiconductor process technologies for its PPA (power, performance and area scaling) as well as time-to-market and time-to-volume. TSMC’s N3 process technology was designed from the very beginning to enable the bespoke combination of FIN configurations. Working closely with our EDA partners, we will enable our customers to take full advantage of TSMC FINFLEX™ in their products by using the same toolset. TSMC FINFLEX™ further extends N3’s PPA leadership and offers the widest and most flexible design envelope for any product in the 3-nanometer generation.
Diagram 3: An illustration of a 3-2 FIN configuration enabled by N3 with FINFLEX
Contributors and Co-Authors:
- Godfrey Cheng, Head of Global Marketing
- Michael Wu, VP, R&D
- Lipen Yuan, Senior Director, Advanced Technology, BD